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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3device_typeregclock-frequencyclock-latencyclocksoperating-points-v2#cooling-cellscpu-supplyphandle#clock-cellsclock-output-namesclock-names#phy-cellsinterrupt-parentinterruptsinterrupt-affinityremote-endpointslave-modefsl,tempmonnvmem-cellsnvmem-cell-namesrangescpu#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangespinctrl-namespinctrl-0fsl,ext-reset-outputstatusfsl,input-selfsl,pinsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitregmapvaluemasklinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supplyvref-supply#pwm-cellscs-gpiosspi-max-frequencypendown-gpioti,x-minti,x-maxti,y-minti,y-maxti,pressure-maxti,x-plate-ohmsassigned-clocksassigned-clock-parents#sound-dai-cellsdma-namesdmasxceiver-supplyregulator-boot-onregulator-always-onregulator-ramp-delaywlf,shared-lrclkuart-has-rtsctsfsl,usbphyfsl,usbmiscphy-clkgate-delay-usvbus-supplyphy_typedr_mode#index-cellsbus-widthcd-gpioswp-gpioskeep-power-in-suspendpinctrl-1pinctrl-2non-removablevmmc-supplyfsl,tuning-stepassigned-clock-rates#dma-cellsfsl,sdma-ram-script-nameinterrupt-namesfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetphy-reset-gpiosreg-namesbus-rangenum-lanesinterrupt-map-maskinterrupt-mapfsl,max-link-speedpower-domainsresetsreset-namesreset-gpiodma-channelsarm,primecell-periphidopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendlabellinux,codegpio-sckgpio-mosinum-chipselectsregisters-numberenable-active-highstartup-delay-uspwmsbrightness-levelsdefault-brightness-levelbacklight